The field of the present invention relates to electronic design automation and, more particularly, to methods and systems for timing analysis of electronic circuit blocks.
Advances in silicon technology increasingly allow larger and more complex designs to be formed on a single chip. Designs may consist of millions or tens of millions of transistors on a single chip. At the same time, however, market demands continue to push designers to develop designs more rapidly and efficiently. A recent trend to increase design speed and efficiency involves the re-use or recycling of electronic circuit blocks or subsystems, commonly referred to as xe2x80x9ccoresxe2x80x9d or xe2x80x9cIPsxe2x80x9d (for xe2x80x9cIntellectual Propertiesxe2x80x9d), hereinafter referred to for convenience as xe2x80x9cvirtual component blocksxe2x80x9d or xe2x80x9cVCs.xe2x80x9d Once the design for a virtual component block has been tested and verified, it can be re-used in other applications which may be completely distinct from the application which led to its original creation. For example, a subsystem for a cellular phone ASIC may contain a micro-controller as well as a digital signal processor and other components. After the design for the cellular phone subsystem has been tested and verified, it could be re-used (as a virtual component block) in, for example, an automotive application. Design reuse of virtual component blocks allows a designer to complete a design much faster than building the entire design from scratch, and avoids the need for debugging, testing and verification of the subsystems embodied in the virtual component block.
While virtual components have been found to be convenient for expediting and simplifying the circuit design process, the successful use of virtual component blocks hinges on the ability to accurately characterize their timing and functionality. A number of techniques have been developed or proposed for performing timing analyses on virtual component blocks, including static timing analysis and functional timing analysis.
Static timing analysis involves the calculation of a worst-case structural (or topological) delay between a circuit""s input and outputs, but ignores the functionality of the circuit. Static timing analysis methods make no attempt to detect false paths, which are signal paths never sensitized (activated) in actual operation. The use of functional information to improve the accuracy of static timing analysis methods has been proposed in the pastxe2x80x94for example, in P. McGeer et al, Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications, Kluwer Academic Publishers (Hingham, Mass. 1991).
Functional timing analysis methods attempt to rely on the fact that the delays in a circuit are linked to the way a circuit functions. xe2x80x9cFunctionalityxe2x80x9d in this context refers to the logical value computed for each circuit node, given an input vector. Unlike traditional static timing analysis, functional timing analysis uses a circuit""s function as well as its structure to characterize delays and timing constraints.
Two widely used methods for functional timing analysis are symbolic analysis via binary-decision diagrams (BDDs), and Boolean search methodologies that systematically enumerate the input space. Both methods assume that the delays of a circuit depend on the values of all of its inputs. These methods aim at finding an input vector that sensitizes the true longest path. However, they both have the disadvantage that their complexity increases exponentially with circuit size, limiting their applicability, or requiring unacceptably large amounts of computation resources for larger circuit designs.
A more practical approach is to assume that a circuit""s delays depend on only a subset of its inputs. This is typical of datapath circuits, where a small number of control inputs determine the delays between a large number of data inputs and data outputs. A simple example is shown by a circuit 50 in FIG. 1, wherein the control inputs 60 to a large extent determine the delays between the data inputs 55 and the data outputs 70.
Methods of timing analysis have been developed based upon the recognition that the control inputs play a role in determining the delays between the data inputs and outputs. These methods generally trade accuracy for computation efficiency. For example, some static timing analyzers employ a systematic case analysis capability whereby the user sets some inputs to constant values prior to performing the timing analysis. A drawback with such timing analysis methods is that they suffer from delay underestimation. Delay underestimation is a serious problem in circuit design because it can lead to incorrect operation.
One timing analysis model involves calculation of the delay in a so-called xe2x80x9cfloating modexe2x80x9d of operation. In a floating mode of operation, each circuit node initially has an unknown value. Upon the application of an input vector to the circuit, the circuit node undergoes a series of transitions or events before it eventually stabilizes at a value determined by the circuit""s internal static functionality.
Examples of event propagation using principles of xe2x80x9ccontrollingxe2x80x9d and xe2x80x9cnon-controllingxe2x80x9d values are illustrated in FIGS. 2A and 2B, for the simple case of a two-input AND gate. A controlling value (CV) at a gate input is one that determines the output of the gate regardless of the values of the other inputs. A non-controlling value (NCV) does not change the gate output by itself. For an AND gate, the controlling and non-controlling values are 0 and 1, respectively. The arrival time of a gate output is determined by the earliest input with a controlling value, if it exists; otherwise, the latest input with the non-controlling value determines the output arrival time. In FIG. 2A, input xe2x80x9caxe2x80x9d is a controlling value because it will eventually become 0, whereas in FIG. 2B, neither input xe2x80x9caxe2x80x9d nor xe2x80x9cbxe2x80x9d is a controlling value because both will stay at 1. Because, input xe2x80x9caxe2x80x9d has a controlling value in FIG. 2A, the gate output arrival time xe2x80x9cTzxe2x80x9d is determined only by the arrival time Ta of input xe2x80x9caxe2x80x9d, plus the gate delay d. In FIG. 2B, however, because neither input xe2x80x9caxe2x80x9d nor xe2x80x9cbxe2x80x9d has a controlling value, the output arrival time Tz is given by the latest input arrival time (in this example, Tb) plus the gate delay d. Because the last arriving event at any node determines the delay up to that node, the terms xe2x80x9carrival timexe2x80x9d and xe2x80x9cdelayxe2x80x9d are used interchangeably herein.
For a generic gate having inputs xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d and output xe2x80x9czxe2x80x9d in floating mode (FM), these concepts may be shown in the form of a truth table, TzFM, such as appearing in Table 1 below.
It is possible to write a logical expression (or predicate) that describes whether an input event propagates from a gate input to the gate output; such expressions are sometimes referred to as xe2x80x9csensitization conditions.xe2x80x9d Referring back to FIGS. 2A and 2B, the sensitization condition for the path from input xe2x80x9cbxe2x80x9d to gate output xe2x80x9czxe2x80x9d may be denoted CONDbz. In FIG. 2A, this path is xe2x80x9csensitizedxe2x80x9d so that CONDbz is 1 (true). In FIG. 2B, this path is not xe2x80x9csensitizedxe2x80x9d so that CONDbz is 0 (false). A number of sensitization conditions have been proposed. Two such sensitization conditions, referred to as xe2x80x9cviabilityxe2x80x9d and xe2x80x9cfloating-mode condition,xe2x80x9d have been used in calculating the floating-mode arrival time of Table 1. The values of TzFM shown in Table 1 are the least pessimistic that can be achieved in xe2x80x9cfloating mode.xe2x80x9d Thus, for any conditional expression Tzx to be correct for delay calculation using the conventional xe2x80x9cfloating modexe2x80x9d conditional analysis, it must exceed the delay values expressed in Table 1 above; that is, it must satisfy the relationship:
Txzxe2x89xa7TzFM ∀xcexdaxe2x80x2∀xcexdb
Several other sensitization conditions have been proposed. xe2x80x9cStatic sensitizationxe2x80x9d is a commonly used sensitization condition which has arisen from test generation. Static sensitization is based on the premise that a path is xe2x80x9csensitizedxe2x80x9d only if all its side inputs (i.e., inputs of a gate that are not on the delay path) have non-controlling values. A computational advantage of this condition is that it depends only on the final (stable) values of the inputs and is independent of the input event times. However, a drawback of static sensitization techniques is that, if the two inputs of a gate are controlling, they incorrectly assume that the paths from both inputs are false.
In contrast to static sensitization, the simplest (but most pessimistic) path sensitization condition is that of topological analysis where events always propagate. Thus, for the two-input gate case, the output arrival time, which may be designated TzTOP, is always the maximum of the input event times plus the gate delay. Table 2 below summarizes and compares the arrival times for floating mode, static sensitization, and topological analysis.
In Table 2, the term xe2x80x9cxe2x88x92∞xe2x80x9d indicates that no event propagates; hence, an effectively xe2x80x9cinfinitexe2x80x9d delay. As may be observed from viewing Table 2, the output arrival time TzTOP under a topological analysis where events always propagate is always greater than or equal to the output arrival time TzFM using floating mode conditional analysis. Topological analysis is commonly used in static timing analysis tools. A big disadvantage is its failure to detect any false paths, leading to overly pessimistic results.
A need exists for a functional timing analysis of circuit blocks that has improved accuracy, yet is not computationally burdensome.
The invention provides in one aspect systems and methods for performing a timing analysis on virtual component blocks or other circuit models by using functional information obtained from the circuit""s control inputs and their useful combinations. A useful technique for condensing time delay information (whether scalar or tabular in form) is also provided, to simplify timing characterization of a virtual component block or circuit model.
A circuit block may have a number of connected gates, a set of control inputs, a set of data inputs, and a set of outputs which are coupled to the control and data inputs along various paths through gates or other circuit elements. In one embodiment, a system and method are provided whereby control inputs and data inputs for a circuit block are identified, along with the functionally meaningful or useful combinations of control inputs. Each functionally meaningful or useful control input combination is applied to the circuit block, and the topological delay for the data inputs are determined only along the paths that are not blocked by the control inputs. The delays along paths that are blocked are ignored. By limiting timing delay analysis to the control input combinations that are functionally meaningful or useful, a timing model results that more accurately reflects true performance of the circuit, in contrast to timing delay analyses that do not account for circuit functionality. A preferred timing delay analysis is further augmented by determining the topological delay for all paths originating at control inputs, without regard to blocking of paths, so as to reduce the chance for possible underestimation of delays from the data inputs. A final timing model may include the combination of maximum delays along data paths for each combination of control inputs, and maximum delays along paths originating from each of the control inputs. The delay analysis may account for different input slews and load capacitances, and the results may be expressed in tabular or matrix form. The functional timing analysis described herein may be embodied in a software program effectuating the methodology of such a timing analysis.
In a separate and distinct aspect of the invention, timing delay information may be condensed or reduced to simplify the timing characterization of a circuit block. Delays may be expressed, for example, in tables or matrixes having entries corresponding to specified input slew and load capacitance combinations. Tables or matrixes that are xe2x80x9cclosexe2x80x9d (i.e., within a specified tolerance) may be combined into a single table or matrix. Table merging results in a smaller number of tables based upon the original set of delay tables, thereby ensuring that the reduced model accurately represents the circuit timing delays (within the specified tolerance). Table reduction according to the techniques described herein may be applied to any set of tables (preferably having the same dimensions), and is not limited to tables defining timing models, but may be applicable to other types of tables as well.
Further embodiments, variations, modifications and enhancements are also described herein.